Amplifier and driving circuit using the same

ABSTRACT

An amplifier in an embodiment of the present invention has MOS transistors connected serially between a power supply VDD and a ground terminal GND; an output terminal Vout connected to a node provided between the MOS transistors; a first mirror capacity provided between the gate of a MOS transistor and the output terminal Vout; and a second mirror capacity provided between the gate of another MOS transistor and the output terminal Vout. The amplifier further includes a first switching circuit for connecting one end of the first mirror capacity to the power supply terminal VDD or to the gate of a MOS transistor; and a second switching circuit for connecting one end of the second mirror capacity to the ground terminal GND or to the gate of another MOS transistor.

FIELD OF THE INVENTION

The present invention relates to an amplifier for driving a capacitiveload such as a liquid crystal display and a driving circuit that usesthe amplifier.

BACKGROUND OF THE INVENTION

Recently, flat panel displays such as liquid crystal displays have beenconsidered to be important items more and more for the progress of theenhanced video and information oriented society and for the wide spreadof multimedia systems. Because those liquid crystal displays have suchmerits as low power consumption, thin and light structure, etc., theyare employed widely as displays of portable terminal devices, etc.

A liquid crystal display has a liquid crystal panel for displayingimages and a driving circuit for driving the liquid crystal panel. Anactive matrix type liquid crystal panel has an element substrate, acounter substrate, and liquid crystal held between those substrates. Onthe element substrate are formed horizontal scanning lines and verticaldata lines respectively. And plural pixel electrodes are formed like amatrix between those scanning and data lines. An active element such asa TFT (Thin Film Transistor) is provided around each node of thosescanning and data lines. Each TFT gate electrode is connected to ascanning line, each source electrode is connected to a data line, andeach drain electrode is connected to a pixel electrode respectively.

Common electrodes facing a pixel electrode are formed on the countersubstrate. One end of a liquid crystal capacity, which is a capacitiveload, is connected to a pixel electrode. The other end of the liquidcrystal capacity is connected to a common electrode facing a pixelelectrode formed on the counter substrate. Consequently, the liquidcrystal capacity is connected equivalently to a TFT drain electrode.

A scanning line driving circuit is connected to the scanning lines and adata line driving circuit is connected to the data lines respectively.The scanning line driving circuit scans the scanning lines sequentiallyfrom up to down to enable the data line driving circuit to apply avoltage to each pixel electrode through a TFT. The common electrodedriving circuit applies a proper voltage to each common electrode. Thisis why the liquid crystal is applied a voltage equivalent to a potentialdifference between the pixel electrode and the common electrode. Theliquid crystal display changes such a voltage applied to the liquidcrystal to change the ordering of the liquid crystal and changes thelight transmittance to make a gradation display.

In the case of a known liquid crystal display, the polarity of a voltageapplied to each pixel electrode from a data line through a TFT(hereinafter, to be referred to as a pixel voltage) is inverted at everypredetermined period. By inverting the polarity of such a voltageapplied to the liquid crystal to make AC driving, the degradation of thecharacteristics of the liquid crystal to be caused by DC driving issuppressed. As an AC driving method, for example, there is a well knowndot inversion driving method, which inverts the polarity of the pixelvoltage with respect to each pixel.

Generally, an operational amplifier subjected to voltage followerconnection is used as an output circuit used as a driving circuitemployed for a liquid crystal display. The frequency characteristic ofthe operational amplifier changes according to a change of the drivingload condition. If the load frequency characteristic changes in theoperational amplifier employed for a driving circuit, the operationalamplifier comes to oscillate, thereby causing a trouble in the displayof the liquid crystal panel.

There are some known methods for improving the frequency characteristicof the operational amplifier and one of the methods is phasecompensation (hereinafter, to be referred to as mirror compensation)realized with use of a mirror capacity (e.g., Laid open Japaneseapplication No. 2005-124120 A). FIG. 9 shows a configuration of aconventional driving circuit 10 described in the JP 2005-124120 A. Asshown in FIG. 9, the conventional driving circuit 100 has anN receivingdifferential amplifier 101, a P receiving differential amplifier 102,and an AB class amplifying circuit 103. The driving circuit of theliquid crystal display described in the JP 2005-124120 A uses the ABclass amplifier 103 for making mirror compensation for enablingRail-to-Rail inputs/outputs.

The AB class amplification circuit 13 has a P channel MOS transistor 104connected between an output terminal and a power supply terminal and anN receiving channel output MOS transistor 105 connected between theoutput terminal and a ground terminal. The gate of the P channel MOStransistor 104 is connected to an output line of the N receivingdifferential amplifier 101. The gate of the N channel MOS transistor 105is connected to an output line of the P receiving differential amplifier105. In the AB class output circuit 103, a pair of mirror capacities 106and 107 for phase compensation are connected between the gate of each ofa pair of P channel MOS transistors 104 and an output terminal Vout andbetween the gate of each of a pair of N channel output MOS transistors105 and the output terminal Vout respectively.

This pair of mirror capacities 106 and 107 is effective to improve thefrequency characteristic of the differential type AB amplifier 1. Inthis case, the larger the mirror capacity, which is assumed to be aphase compensation capacity, is, the more the frequency characteristicis improved.

If a driving circuit including an operational amplifier for mirrorcompensation, which enables Rail-to-Rail inputs/outputs, is used for theAC driving that inverts the voltage polarity alternately just like theabove described dot inversion driving method, the following cases willarise in each polarity inversion, thereby the through-current increases.As a result, the through-rate of the operational amplifier is lowered.This has been a conventional problem.

(1) When Polarity Output is Inverted from Positive to Negative

If the polarity of the polarity inverted signal is inverted frompositive to negative, the gate voltage rises at each of the P channelMOS transistor 104 and the N channel MOS transistor 105. As a result,the ON resistance of the P channel MOS transistor 104 rises while the ONresistance of the N channel MOS transistor 105 falls, then the Voutfalls. At the moment when the polarity of this Vout is inverted frompositive to negative, the Vout makes a voltage fall suddenly, therebythe charge goes to the mirror capacity 106. Consequently, the gatevoltage of the P channel MOS transistor 104 falls and its ON resistanceis delayed to rise. Therefore, at such a polarity inversion frompositive to negative, the ON resistance of both P channel MOS transistor104 and N channel MOS transistor 105 is lowered at the same time in aperiod, in which a large through-current comes to flow.

(2) When Polarity Output is Inverted from Negative to Positive

If the polarity of the polarity inverted signal is inverted fromnegative to positive, the gate voltage falls at both the P channel MOStransistor 104 and the N channel MOS transistor 105. As a result, the ONresistance of the P channel MOS transistor 104 falls while the ONresistance of the N channel MOS transistor 105 rises, then the Voutrises. At the moment when the polarity of this Vout is inverted fromnegative to positive, the Vout makes a voltage rise suddenly, therebythe charge goes to the mirror capacity 106. Consequently, the gatevoltage of the N channel MOS transistor 105 rises and its ON resistanceis delayed to rise. Therefore, even at such a polarity inverted outputfrom negative to positive, the ON resistance of both P channel MOStransistor 104 and N channel MOS transistor 105 is lowered at the sametime in a period, in which a large through-current comes to flow.

If AC driving is adopted for a liquid crystal panel such way, theoperational amplifier in the driving circuit keeps inverting the outputvoltage to drive the liquid crystal, which is a capacitive load. In thatcase, each time the output voltage polarity is inverted, the outputvoltage comes to amplitude significantly. And to obtain a desired outputvoltage when the output voltage polarity is inverted, the ON resistanceof one of the transistors 104 and 105 is lowered and the ON resistanceof the other transistor is raised. In the case of the conventionalmirror compensation, the output of the operational amplifier comes toaffect the gate of each output transistor due to the mirror capacity.Consequently, the mirror capacity causes a delay of the rising of the ONresistance of the transistor that is expected to increase the ONresistance to limit the output. As a result, the ON resistance of bothtransistors 104 and 105 falls at the same time in a period, thereby thethrough-current increases and the through rate of the operationalamplifier is lowered. And such an increase of the through-current causesheat generation and EMI (Electro-Magnetic Interference) in chips.

SUMMARY

In one aspect of the amplifier of the present invention, the amplifierhas first and second output transistors connected serially between afirst power supply potential and a second power supply potential; anoutput terminal connected to a node between the first and secondtransistors; a first capacity element provided between a controlterminal of the first transistor and the output terminal; a secondcapacity element provided between a control terminal of the secondtransistor and the output terminal; a first switching circuit forconnecting one end of the first capacity element to the first powersupply potential or to the control terminal of the first transistor; anda second switching circuit for connecting one end of the second capacityelement to the second power supply potential or to the control terminalof the second transistor.

With such a configuration, each switching circuit comes to able todisconnect a phase compensation capacity from the gate of each outputtransistor at a large change of an output voltage. Consequently, the ONresistance of an output transistor disconnected from a phasecompensation capacity is prevented from lowering, thereby the throughcurrent can be reduced. This is why the through-rate of the operationalamplifier can be suppressed effectively.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description ofcertain preferred embodiments taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a configuration of an operational amplifier in a firstembodiment;

FIG. 2 is a configuration of a driving circuit in the first embodiment;

FIG. 3 is a configuration of a liquid crystal display that uses thedriving circuit in the first embodiment;

FIG. 4 is a configuration of a switch control circuit used for thedriving circuit in the first embodiment;

FIG. 5 is a diagram for describing an operation of the driving circuitin the first embodiment;

FIG. 6 is another diagram for describing the operation of the drivingcircuit in the first embodiment;

FIG. 7 is a configuration of an operational amplifier in a secondembodiment;

FIG. 8 is a configuration of an operational amplifier in a thirdembodiment; and

FIG. 9 is a configuration of a conventional operational amplifier.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

Hereunder, an operational amplifier in a first embodiment of the presentinvention will be described with reference to FIG. 1. As shown in FIG.1, the operational amplifier in this first embodiment has an N receivingdifferential amplifier 1 and a P receiving differential amplifier 2, andan AB class output circuit 3.

The N receiving differential amplifier 1 has an inverted input terminal(−) and a noninverted input terminal (+). As a concrete configuration,for example, as shown in the conventional one in FIG. 9, the operationalamplifier may have a general configuration including a pair of N channeldifferential MOS transistors, a pair of current mirror type P channelload MOS transistors connected to the pair of N channel differential MOStransistors, an N channel constant current source MOS transistor forinputting an N channel differential bias voltage to the gates andsupplying a constant current to the sources of the pair of the N channeldifferential MOS transistors respectively. An output terminal of the Nreceiving differential amplifier 1 is connected to the gate of the Pchannel output MOS transistor 14 of the AB class output circuit 3. The Nreceiving differential amplifier 1 outputs an inputted signal to thegate of the P channel output MOS transistor 14 of the AB class outputcircuit 3.

The P receiving differential amplifier 2 has an inverted input terminal(−) and a noninverted input terminal (+). As a concrete configuration,the P receiving differential amplifier 2 may have a generalconfiguration, for example, like the conventional example as shown inFIG. 9. In that case, the amplifier 2 comes to have a pair of P channeldifferential MOS transistors, a pair of current mirror type N channelload MOS transistors connected to the pair of P channel differential MOStransistors, a P channel constant current source MOS transistor forinputting a P channel differential bias voltage to the gates andsupplying a constant current to the sources of the pair of P channeldifferential MOS transistors respectively. An output terminal of the Preceiving differential amplifier 2 is connected, to the gate of the Nchannel output MOS transistor 15 of the AB class output circuit 3. The Preceiving differential Amplifier 2 outputs an inputted signal to thegate of the N channel output MOS transistor 15 of the AB class outputcircuit 3.

The AB class output circuit 3 has a P channel constant current MOStransistor 10, an AB class amplification circuit 13, a P channel shiftMOS transistor 11, an N channel shift MOS transistor 12, a P channeloutput MOS transistor 14, an N channel output MOS transistor 15(hereinafter, to be abbreviated as MOS transistors 10 to 15 as needed),a first switching circuit 4, a second switching circuit 5, a firstmirror capacity (first capacity element) 31, and a second mirrorcapacity (second capacity element) 32. The first switching circuit 4 hasa first control switch 20 and a second control switch 21. The secondswitching circuit 5 has a third control switch 22 and a fourth controlswitch 23. The configuration is not limited only to that shown in FIG.1; the configuration may be determined freely if it includes the controlswitches 20 to 23 and the mirror capacities 31 and 32 described above.

In the AB class output circuit in this first embodiment, the pair ofmirror capacities 31 and 32 used for phase compensation are connectedbetween each gate of the pair of P/N channel output MOS transistors 4and 5 and the output terminal Vout. Consequently, the differential classAB amplifier 3 comes to have a favorable frequency characteristic.

In the AB amplifier 3, MOS transistors 10 to 13 are provided at the sideof the N and P receiving differential amplifiers 1 and 2 respectively.The MOS transistor 10 is connected between an output line 6 of the Nreceiving differential amplifier 1 and a power supply terminal (firstpower supply potential) VDD. A P channel constant current bias voltageBP2 is inputted to the gate of the MOS transistor 10. The MOS transistor13 is connected between an output line 7 of the P receiving differentialamplifier 2 and a ground terminal (second power supply potential) GND.An N channel constant current bias voltage BN2 is inputted to the gateof the MOS transistor 13.

The MOS transistors 11 and 12 function as level shifters. The MOStransistors 11 and 12 are connected in parallel between the output lines6 and 7 of the pair of N and P receiving differential amplifiers 1 and2. A P channel constant current bias voltage BP3 is inputted to the gateof the MOS transistor 11. An N channel bias voltage BN3 is inputted tothe gate of the MOS transistor 12.

In the AB class output circuit, the first and second switching circuits4 and 5, as well as the first and second mirror capacities 31 and 32 areprovided at the output side of the MOS transistors 10 to 13. The firstmirror capacity 31 is provided between the output line 6 of the Nreceiving differential amplifier 1 and the power supply terminal VDD. Inother words, one end of the first mirror capacity 31 is connected to theoutput line 6 of the N receiving differential amplifier 1 or to thepower supply terminal VDD and the other end thereof is connected to theoutput terminal Vout. And the second mirror capacity 32 is providedbetween the output line 7 of the P receiving differential amplifier2/the ground GND and the output terminal Vout. In other words, one endof the first mirror capacity 32 is connected to the output line 7 of theP receiving differential amplifier 2 or to the ground terminal GND andthe other end thereof is connected to the output terminal Vout.

The first switching circuit 4 switches and connects one end of the firstmirror capacity 31 to the output line 6 of the N receiving differentialamplifier 1 or to the power supply terminal VDD. The first switchingcircuit 4 has first and second control switches 20 and 21. One end ofthe first control switch 20 is connected to the output line 6 of the Nreceiving differential amplifier 1 and the other end thereof isconnected to one end of the first mirror capacity 31. One end of thesecond control switch 21 is connected to the power supply terminal VDDand the other end thereof is connected to one end of the first mirrorcapacity 31. Due to the switching operation of those control switches 20and 21, the first switching circuit 4 connects one end of the firstmirror capacity 31 to the output line 6 of the N receiving differentialamplifier 1 or to the power supply terminal VDD.

The second switching circuit 5 switches and connects one end of thesecond mirror capacity 32 to the output line 7 of the P receivingdifferential amplifier 2 or to the ground terminal GND. The secondswitching circuit 5 has third and fourth control switches 22 and 23. Oneend of the third control switch 22 is connected to the output line 7 ofthe P receiving differential amplifier 2 and the other end thereof isconnected to one end of the second mirror capacity 32. One end of thefourth control switch 23 is connected to the ground terminal GND and theother end thereof is connected to one end of the second mirror capacity32. Due to the switching operation of those control switches 22 and 23,the second switching circuit 5 connects one end of the first mirrorcapacity 32 to the output line 7 of the P receiving differentialamplifier 2 or to the ground terminal GND. The operation of thosecontrol switches will be described in detail later.

In the AB class output circuit 3, MOS transistors 14 and 15 are providedat the output side of the first and second switching circuits 4 and 5.One end of the main current path of each of the MOS transistors 14 and15 is connected to a common node. The common node of the MOS transistors14 and 15 is connected to the output terminal Vout. The gate of the MOStransistor 14 is connected to the output line 6 of the N receivingdifferential amplifier 1. One end of the main current path of the MOStransistor 14 is connected to the output terminal Vout and the other endthereof is connected to the power supply VDD. Consequently, the MOStransistor 14 is connected between the output terminal Vout and thepower supply terminal VDD. The gate of the MOS transistor 15 isconnected to the output line 7 of the P receiving differential amplifier2. One end of the main current path of the MOS transistor 15 isconnected to the output terminal Vout and the other end thereof isconnected to the ground terminal GND. Consequently, the MOS transistor15 is connected between the output terminal Vout and the ground terminalGND. In other words, the MOS transistors 14 and 15 are connectedserially between the power supply terminal VDD and the ground terminalGND. The output terminal Vout is connected to a node provided betweenthe MOS transistors 14 and 15.

Consequently, the first mirror capacity 31 is provided between the gateof the MOS transistor 14 and the output terminal Vout. And the secondmirror capacity 32 is provided between the gate of the MOS transistor 15and the output terminal Vout. The first switching circuit 4 connects oneend of the first mirror capacity 31 to the power supply terminal VDD orto the gate of the MOS transistor 14. The second switching circuit 15connects one end of the second mirror capacity 32 to the ground terminalGND or to the gate of the MOS transistor 15.

Next, a driving circuit shown in FIG. 2 will be described with referenceto FIG. 2. The driving circuit is connected to the plurality ofoperational amplifiers shown in FIG. 1, which are subjected to voltagefollower connection. FIG. 2 shows a configuration of the driving circuitin this embodiment. In FIG. 2, the same reference numerals represent thesame configuration elements as those shown in FIG. 1, avoiding redundantdescription. As shown in FIG. 2, the output of the output terminal Voutis inputted to the inverted input terminals (−) of the N receivingdifferential amplifier 1 and P receiving differential amplifier 2respectively. The driving circuit in this embodiment is used favorablyto drive the data lines of a liquid crystal panel. Hereunder, thisdriving circuit is referred to as a data line driving circuit 8.Although only one operational amplifier is shown here, actually pluraloperational amplifiers are provided in parallel in accordance with thenumber of data lines of the subject liquid crystal panel. Although notshown in FIG. 2, the data line driving circuit 8 has a control circuitfor controlling the control switches 20 to 23. The control circuit willbe described in detail later.

A gradation voltage is inputted to the noninverted input terminals (+)of the N receiving differential amplifier 1 and the P receivingdifferential amplifier 2 from a Vin terminal (+), respectively. If apositive polarity gradation voltage is inputted to the Vin (+) terminal,the N receiving differential amplifier 1 lowers the gate voltage of theMOS transistor 14. On the other hand, the P receiving differentialamplifier 2 lowers the gate voltage of the MOS transistor 15.Consequently, the ON resistance of the MOS transistor 14 falls and theON resistance of the MOS transistor 15 rises. Thus the output terminalVout outputs a positive polarity gradation voltage.

If a negative polarity is inputted to the Vin (+) terminal, the Nreceiving differential amplifier 1 raises the gate voltage of the MOStransistor 14. On the other hand, the P receiving differential amplifier2 raises the gate voltage of the MOS transistor 15. Consequently, the ONresistance of the MOS transistor 14 rises and the ON resistance of theMOS transistor 15 falls. Thus the output terminal Vout outputs anegative polarity gradation voltage.

Next, a description will be made for a configuration of a liquid crystaldisplay that uses the driving circuit described in this embodiment withreference to FIG. 3. As shown in FIG. 3, the data line driving circuit 8in this embodiment can be connected from external to the liquid crystalpanel 9. The data line driving circuit 8 may also be formed on thesubstrate of the liquid crystal panel 9 connectably to all the datalines SL.

The liquid crystal panel 9 has a display area consisting of pluralpixels. The liquid crystal panel 9 holds liquid crystal between a TFT(Thin Film Transistor) array substrate (not shown) and a countersubstrate (not shown) disposed to face the TFT array substrate. The TFTarray substrate has horizontal scanning lines GL and vertical data linesSL and a TFT is provided at each node of those scanning lines GL anddata lines SL. And plural pixel electrodes are formed and disposed likea matrix between the scanning lines GL and the data lines SL. The TFTgate electrodes are connected to the scanning lines GL and the TFTsource electrodes are connected to the data lines SL respectively.Consequently, one of the liquid crystal capacities held between thepixel electrodes and the common electrodes comes to be connected to theTFT drain electrodes (pixel electrodes) and the other liquid crystalcapacity comes to be connected to the common electrodes.

Common electrodes, as well as R (red), G (green), and (B (blue) colorfilters are formed on the counter substrate. Actually, the commonelectrodes are transparent electrodes formed almost all over the countersubstrate so as to face the pixel electrodes respectively. A scanningsignal is supplied to each of the scanning lines GL and the scanningsignal turns on all the TFTs connected to one selected scanning line GLsimultaneously. And a gradation voltage is supplied to each data line SLand the pixel electrodes are charged according to the gradation voltage.

According to a potential difference between each pixel electrode inwhich a gradation voltage is written and each common electrode, theordering of the liquid crystal between the pixel electrode and thecommon electrode changes. Consequently, the amount of the transmittedlight irradiated from a back light (not shown) is controlled. Each pixelof the liquid crystal panel 9 displays in various colors matching with ashade of color in accordance with the transmitted light volume and anyof the display RGB color displays. In a monochrome display mode, nocolor filters are required.

In this embodiment, a 2-line dot inversion driving method is adopted. Inother words, the polarity of a display signal supplied to a pixelelectrode is inverted for each data line SL alternately and inverted forevery second scanning line GL. The polarity of each display signal isswitched for each frame. The polarity status “positive(+)” means thatthe potential of a display signal supplied from a data line is over thecommon electrode potential that is a reference potential and the“negative(−)” status means that the display signal potential is underthe common electrode potential.

The data line driving circuit 8 in this first embodiment outputs theabove described gradation voltage according to each display signalsupplied from external. As known widely, the data line driving circuit 8has a shift register circuit, a latch circuit, a gradation voltagegeneration circuit, etc. They are omitted in FIGS. 2 and 3. In the caseof inverted driving as described above, positive and negative polaritysignals are inputted to the data line driving circuit 8 as displaysignals. Positive and negative polarity display signals may be a commonsignal and switched between positive and negative in a latch circuit.

As shown in FIG. 3, the data line driving circuit 8 in this firstembodiment has a control circuit 60 for controlling the control switches20 to 23. The control circuit 60 turns on/off the control switches 20 to23 according to the inputted polarity inverted signal POL. Hereunder, aconfiguration of the control circuit 60 will be described with referenceto FIG. 4. As shown in FIG. 4, the control circuit 60 has first andsecond flip-flop circuits 61 and 62, first and second AND circuits 63and 64, an OR circuit 65, as well as third and fourth AND circuits 66and 67. Here, a case in which a D type flip-flop circuit is employedwill be described.

A polarity inverted signal POL (a) is inputted to an input terminal D ofthe first flip-flop circuit 61 and a strobe signal STB is inputted to aninput terminal K thereof. An output (b) of the first flip-flop circuit61 is inputted to an input terminal D of the second flip-flop circuit 62and one of the two input terminals of the first AND circuit 63. And astrobe signal STB is inputted to an input terminal K of the secondflip-flop circuit 62.

The output (b) of the first flip-flop circuit 61 is inverted andinputted to one of the two input terminals of the second AND circuit 64.An output (c) of the second flip-flop circuit 62 is inverted andinputted to the other input terminal of the first AND circuit 63. Theoutput (c) of the second flip-flop circuit 62 is inputted to the otherinput terminal of the second AND circuit 64. The outputs of the firstand second AND circuits 63 and 64 are inputted to an input terminal ofthe OR circuit 65 respectively.

An output (d) of the OR circuit 65 is inputted to the one of the twoinput terminals of each of the third and fourth AND circuits 66 and 67.A polarity inverted signal POL(e) is inputted to the other inputterminal of the third AND circuit 66. A polarity inverted signal POL(f)inverted by an inverter is inputted to the other input terminal of thefourth AND circuit 67.

An output (g) of the third AND circuit 66 is inputted to the fourthcontrol switch 23, then inverted by an inverter and inputted to thethird control switch 22. An output (h) of the fourth AND circuit 67 isinputted to the second control switch 21, then inverted by an inverterand inputted to the first control switch 20.

A logic circuit denoted by a dotted line A in FIG. 4 outputs a signal(d) on the high level (1) when the polarity inverted signal POL isinverted. Another logic circuit denoted by a dotted line B in FIG. 4 hasoutputs of two systems (g) and (h). When the polarity inverted signalPOL denotes one of logics, the logic circuit B fixes the output of onesystem and changes the output of the other system according to theoutput (d) of the logic circuit A. When the signal POL is on the highlevel, the logic circuit B keeps the output (h) in the previous periodas is. Then the logic circuit B switches the output (g) between highlevel (1) and low level (0) according to the output (d) of the logiccircuit A. On the other hand, when the signal POL is on the low level,the logic circuit B keeps the output (g) in the previous period as is.Then, the logic circuit B switches the output (h) between high level (1)and low level (0) according to the output (d) of the logic circuit A.The configuration of the control circuit 60 is not limited only to thatdescribed so far; it may be varied freely, of course.

Next, the operation of the data line driving circuit 8 in this firstembodiment will be described with reference to FIGS. 5 and 6. FIG. 5shows a timing chart for describing the operation of the data linedriving circuit 8. FIG. 6 shows a truth table of the signal at each ofthe points a to h of the control circuit 60 shown in FIG. 4. As shown inFIG. 5, the operation of the data line driving circuit 8 varies in casesas follows; (1) “polarity output is changed from negative to positive”,(2) “positive polarity output is kept”, (3) “polarity output is changedfrom negative to positive”, and (4) “negative polarity output is kept”.Each of the above cases will be described below. Here, it is assumedthat a 2-line dot inverted driving method is adopted. Consequently, thepolarity of the gradation voltage output from the operational amplifiersin the odd-numbered columns differs from that output from theoperational amplifiers in the even-numbered columns. And eachoperational amplifier outputs a gradation voltage of which polarity isinverted for every second scanning line. In FIG. 5, each of theoperational amplifiers in the odd-numbered columns outputs Vout.

(1) When Polarity Output is Changed from Negative to Positive

In the period (1) shown in FIG. 5, when the polarity inverted signal POLenters the high level at its rising time, a positive polarity gradationvoltage is inputted to the noninverted input terminals (+) of both the Nreceiving differential amplifier 1 and the P receiving differentialamplifier 2 in the odd-numbered columns. On the other hand, a negativepolarity gradation voltage is inputted to the noninverted inputterminals (+) of both the N receiving differential amplifier 1 and the Preceiving differential amplifier 2 in the even-numbered columns.

When the signal POL rises and the strobe signal STB rises and enters thehigh level, the gate voltage of the P channel output MOS transistor 14falls and its ON resistance is lowered. And the gate voltage of the Nchannel output MOS transistor 15 also falls, but its ON resistancerises. Consequently, the Vout voltage output from the operationalamplifier rises. In other words, if an input to an operational amplifieris inverted from positive polarity to negative polarity, the polarity ofthe Vout voltage is inverted from negative to positive.

At that time, the control circuit functions as shown in FIG. 6 to turnon/off the control switches 20 to 23. And as shown in FIG. 6 (1), thelogic circuit A in FIG. 4 outputs the signal (d) of high level (1) whenthe level of the signal POL is changed from low to high. Because thesignal POL is on the high level (1) at that time, the output (h) forcontrolling the first and second control switches 20 and 21 is fixed onthe low level (0) as it has been in the previous period. Consequently,the first control switch 20 is turned on and the second control switch21 is turned off. The output line of the N receiving differentialamplifier 1 is thus connected to one end of the first mirror capacity31. And the power supply terminal VDD is disconnected from one end ofthe first mirror capacity 31.

On the other hand, the output (g) for controlling the third and fourthcontrol switches 22 and 23 is switched between low level (0) and highlevel (1) according to the output of the logic circuit A. Consequently,the third control switch 22 is turned off and the fourth control switch23 is turned on. As a result, the ground terminal GND is connected toone end of the second mirror capacity 32. And the output line of the Preceiving differential amplifier 2 is disconnected from the secondmirror capacity 32.

Because the third control switch is turned off such way, the gate of theN channel output MOS transistor 15 is disconnected from the output ofthe control switch 22. Consequently, the N channel output MOS transistor15 can avoid sudden voltage rising of the Vout to be caused by thepolarity inversion from negative to positive. In other words, when theVout polarity is inverted from negative to positive, no charge goes tothe second mirror capacity 32 from the output line 7. Consequently, thegate voltage of the N channel output MOS transistor 15 rises, therebythe ON resistance rising time is shortened. This is why it is possibleto avoid the conventional problem that the Vout voltage rises suddenlyat the time of polarity inversion from negative to positive, then the ONresistance of the P channel output MOS transistor 14 and the N channeloutput MOS transistor 15 is reduced at the same time, thereby a largethrough-current comes to flow.

Furthermore, when the second mirror capacity 32 is disconnected from thegate of the N channel output MOS transistor 15, the node of the secondmirror capacity 32, having been connected to the gate of the N channeloutput MOS transistor 15, is not opened, but connected to the groundterminal GND. Consequently, it is possible to prevent a conventionalproblem that, when the second mirror capacity 32 is connected to thegate of the next time, the gate voltage becomes unstable.

(2) When Positive Polarity Output is Kept as is

As shown in FIG. 5 (2), if the signal POL is kept on the high level, apositive polarity gradation voltage is kept inputted to the noninvertedinput terminals (+) of both the N receiving differential amplifier 1 andthe P receiving differential amplifier 2 in the odd-numbered columns.And a negative polarity gradation signal is kept inputted to thenoninverted input terminals (+) of both the N receiving differentialamplifier 1 and the P receiving differential amplifier 2 in theeven-numbered columns.

At that time, just like the period (1), the gate voltage of the Pchannel output MOS transistor 14 falls and its ON resistance also falls.And the gate voltage of the N channel output MOS transistor 15 falls,but its ON resistance rises. Consequently, the output terminal Vout ofthe operational amplifier outputs a positive polarity gradation voltage.In other words, if an input to the operational amplifier is kept inpositive polarity, the Vout voltage is kept in positive polarity.

At that time, as shown in FIG. 6 (2), the logic circuit A shown in FIG.4 keeps the signal POL on the high level thereby outputting the lowlevel (0) signal (d). At that time, the signal POL is on the high level(1), so that the output (h) for controlling the first and second controlswitches 20 and 21 is kept on the low level (0) in the previous (1)period. Consequently, the first and second control switches 20 and 21 gointo the same status as that in the (1) period. In other words, thefirst control switch 20 is turned on and the second control switch 21 isturned off. This means that the output line of the N receivingdifferential amplifier 1 is connected to one end of the first mirrorcapacity 31 and the power supply terminal VDD is disconnected from oneend of the first mirror capacity 31.

On the other hand, the output (g) for controlling the third and fourthcontrol switches 22 and 23 is switched between high level (1) and lowlevel (0) according to the output (d) of the logic circuit A.Consequently, the third and fourth control switches 22 and 23 go intothe counter status of the (1) period. In other words, immediately afterthe strobe signal STB rises, the third control switch 22 is turned onand the fourth control switch 23 is turned off. This means that theoutput line of the P receiving differential amplifier 2 is connected toone end of the second mirror capacity 32 and the ground terminal GND isdisconnected from the second mirror capacity 32.

If the input to the operational amplifier is kept as is such way, theVout output voltage never change suddenly. Consequently, the gatevoltage of both the P channel output MOS transistor 14 and the N channeloutput MOS transistor 15 is kept as is. Consequently, the output line ofthe N receiving differential amplifier 1 can be connected to the firstmirror capacity 31 and the output line of the P receiving differentialamplifier 2 can be connected to the second mirror capacity 32respectively to make the same phase compensation as the conventionalone.

(3) When Polarity Output is Changed from Positive to Negative

In the period (3) shown in FIG. 5, if the signal POL falls and goes intothe low level, a negative polarity gradation voltage is inputted to thenoninverted input terminals (+) of both the N receiving differentialamplifier 1 and the P receiving differential amplifier 2 of theoperational amplifiers in the odd-numbered columns. And a positivepolarity gradation signal is inputted to the noninverted input terminals(+) of the N receiving differential amplifier 1 and the P receivingdifferential amplifier 2 of the operational amplifiers in theeven-numbered columns.

If the signal POL and the strobe signal STB rise, then the signal STBgoes into the high level, the gate voltage of the N channel output MOStransistor 15 rises and its ON resistance is lowered. The gate voltageof the P channel output MOS transistor 14 also rises and its ONresistance rises. Consequently, the Vout output voltage from eachoperational amplifier falls. In other words, when the input to theoperational amplifier is inverted from positive polarity to negativepolarity, the Vout voltage polarity is also inverted from positive tonegative.

At that time, as shown in FIG. 6 (3), the logic circuit A in FIG. 4outputs a high level (1) signal (d) when the level of the signal POL isswitched from high to low. At that time, because the signal POL is onthe low level (0), the output (g) for controlling the third and fourthcontrol signals 22 and 23 is fixed on the low level (0) in the previous(2) period. Consequently, the third and fourth control switches 22 and23 goes into the same status as that of the (2) period. This means thatwhen the strobe signal STB rises, the third control switch 22 is turnedon and the fourth control switch 23 is turned off. This also means thatthe output line of the P receiving differential amplifier 2 is connectedto one end of the second mirror capacity 32. And the ground terminal GNDis disconnected from the second mirror capacity 32.

On the other hand, the level of the output (h) for controlling the firstand second control switches 20 and 21 is changed from high (1) to low(0) according to the output (d) of the logic circuit A. Consequently,the first and second control switches 20 and 21 go into the counterstatus of the (2) period. In other words, when the strobe signal STBrises, the first control switch 20 is turned off and the second controlsignals 21 is turned on. This means that the power supply terminal VDDis connected to one end of the first mirror capacity 31 and the outputline of the N receiving differential amplifier 1 is disconnected fromone end of the first mirror capacity 31.

Because the first control switch 20 is turned off such way, the gate ofthe P channel output MOS transistor 14 is disconnected from the output.Consequently, the P channel output MOS transistor 14 can avoid a suddenvoltage drop of the Vout to be caused by the polarity inversion frompositive to negative. This means that when the Vout polarity is invertedfrom positive to negative, no charge goes to the first mirror capacity31. Consequently, the gate voltage of the P channel output MOStransistor 14 falls and its ON resistance rising time can be shortened.This is why it is possible to avoid the conventional problem that the ONresistance of both the P channel output MOS transistor 14 and the Nchannel output MOS transistor 15 is lowered simultaneously due to asudden Vout voltage drop to be caused by polarity inversion frompositive to negative, thereby a large through-current comes to flow.

When the first mirror capacity 31 is disconnected from the gate of the Pchannel output MOS transistor 14, the node to which the gate of thefirst mirror gate 31 is connected is not opened, but connected to thepower supply terminal VDD. Consequently, it is possible to prevent aconventional problem that the gate potential becomes unstable, therebycausing an operation error when the first mirror capacity 31 isconnected to the gate of the P channel output MOS transistor 14 nexttime.

(4) When Negative Polarity Output is Kept as is

As shown in FIG. 5 (4) period, if the signal POL is kept on the lowlevel, a negative polarity gradation voltage is kept inputted to thenoninverted input terminals (+) of the N receiving differentialamplifier 1 and the P receiving differential amplifier 2 of theoperational amplifiers in the odd-numbered columns. And a positivepolarity gradation voltage is kept inputted to the noninverted inputterminals (+) of the N receiving differential amplifier 1 and the Preceiving differential amplifier 2 of the operational amplifiers in theeven-numbered columns.

At that time, if the strobe signal STB rises and goes into the highlevel, the gate voltage of the N channel output MOS transistor 15 risesand the ON resistance of the N channel output MOS transistor 15 fallsjust like in the (3) period. At that time, the gate voltage of the Pchannel output MOS transistor 14 and its ON resistance also rise.Consequently, each of the operational amplifiers outputs a negativepolarity gradation voltage through the output terminal Vout. In otherwords, if the input to the operational amplifier is kept at the negativepolarity, the Vout voltage is also kept at the negative polarity.

At that time, as shown in FIG. 6 (4), the logic circuit A shown in FIG.4 outputs a low level (0) signal (d), since the signal POL is kept onthe low level. At that time, because the signal POL is on the low level(0), the output (g) for controlling the third and fourth controlswitches 22 and 23 is fixed on the low level (0) in the previous period(3). Consequently, the third and fourth control switches 22 and 23 gointo the same status as that in the period (3). In other words, when thestrobe signal STB rises, the third control switch 22 is turned on andthe fourth control switch 23 is turned off. This means that the outputline of the P receiving differential amplifier 2 is connected to one endof the second mirror capacity 32 and the ground terminal GND isdisconnected from the second mirror capacity 32.

On the other hand, the level of the output (h) for controlling the firstand second control switches 20 and 21 is switched from high (1) to low(0) according to the output (d) of the logic circuit A. Consequently,the first and second control switches 20 and 21 go into the counterstatus of that of the (3) period. In other words, the first controlswitch 20 is turned on and the second control switch 21 is turned off.This means that the output line of the N receiving differentialamplifier 1 is connected to one end of the first mirror capacity 31 andthe power supply terminal VDD is disconnected from one end of the firstmirror capacity 31.

Thus the output Vout never makes a sudden change as long as there is nochange in the input to the operational amplifier. Consequently, the gatevoltage of the P channel output MOS transistor 14 and the N channeloutput MOS transistor 15 is kept as is. Consequently, it is possible tomake the same phase compensation as the conventional one by connectingthe output line of the N receiving differential amplifier 1 to the firstmirror capacity 31 and the output line of the P receiving differentialamplifier 2 to the second mirror capacity 32 respectively.

As described above, according to the present invention, one end of thefirst mirror capacity 31 can be switched and connected to the outputline 6 of the N receiving differential amplifier 1 or to the powersupply terminal VDD with use of the first switching circuit 4. And oneend of the second mirror capacity 32 can be switched and connected tothe output line 7 of the P receiving differential amplifier 2 or to theground terminal GND with use of the second switching circuit 5.Consequently, it is possible to suppress an increase of thethrough-current to occur when the polarity of the output gradationvoltage is inverted. And by suppressing the through-current such way,the through-rate of each operational amplifier can be prevented fromlowering.

Second Embodiment

Next, a description will be made for an operational amplifier in asecond embodiment of the present invention with reference to FIG. 7.FIG. 7 is a diagram for describing another configuration of theoperational amplifier in this second embodiment of the presentinvention. In FIG. 7, the same reference numerals represent the sameconfiguration items as those shown in FIG. 1, avoiding redundantdescription.

As shown in FIG. 7, the operational amplifier in this second embodimenthas a N receiving differential amplifier 1, a P receiving differentialamplifier 2, and an AB class output circuit 3. The AB class outputcircuit 3 consists of MOS transistors 10 to 15, control switches 20 to23, mirror capacities 31 and 32, and zero-point erasing resistors 40 and41. This second embodiment differs from the first embodiment shown inFIG. 1 only in that first and second zero-point erasing resistors 41 and42 are provided.

The zero-point erasing resistors 41 and 42 are provided to make the timeconstant greater and improve the frequency characteristic. The firstzero-point erasing resistor 41 is provided between the first controlswitch 20 and the first mirror capacity 31. The second zero-pointerasing resistor 42 is provided between the third control switch 22 andthe second mirror capacity 32. In case where the control switches 20 to23, the mirror capacities 31 and 32, and the zero-point erasingresistors 40 and 41 are included, the configuration of other items suchas the MOS transistors 10 to 15 may not be limited only to theconfiguration of the operational amplifier in this second embodimentshown in FIG. 7. Furthermore, the disposition places of the firstcontrol switch 20 and the zero-point erasing resistor 40 connectedserially, as well as the third control switch 22 and the firstzero-point erasing resistor 41 connected serially may be exchangedrespectively in the configuration shown in FIG. 7.

The operations of the control switches 20 to 23 are as shown in FIG. 5and they are the same as those described in the first embodiment. Evenin this case, as described above, the through-current is suppressed andthe through-rate of the operational amplifier is prevented fromlowering.

Third Embodiment

Next, an operational amplifier in a third embodiment of the presentinvention will be described with reference to FIG. 8. FIG. 8 shows aconfiguration of the operational amplifier in this third embodiment ofthe present invention. In FIG. 8, the same reference numerals representthe same component elements as those shown in FIG. 1, avoiding redundantdescription.

As shown in FIG. 8, the operational amplifier in this third embodimenthas an N receiving differential amplifier 1, a P receiving differentialamplifier 2, and an AB class output circuit 3 just like the first andsecond embodiments described above. The AB class output circuit 3consists of MOS transistors 10 to 15, control switches 20 to 23, mirrorcapacities 31 and 32, and control transistors 50 to 53. In this thirdembodiment, the control switches 20 to 23 employed in the first andsecond embodiments shown in FIG. 1 are replaced with the controltransistors 50 to 53. This is only a difference between this thirdembodiment and other first and second embodiments.

The first switching circuit 4 has first and second control transistors50 and 52. One end of the first control transistor 50 is connected to anoutput line 6 of the N receiving differential amplifier 1 and the otherend thereof is connected to one end of the first mirror capacity 31. Oneend of the second control transistor 51 is connected to a power supplyterminal VDD and the other end thereof is connected to one end of thefirst mirror capacity 31. Those control transistors 50 and 51 areswitched to enable the switching circuit 4 to connect one end of thefirst mirror capacity 31 to the output line 6 of the N receivingdifferential amplifier 1 or to the power supply terminal VDD.Consequently, the first control transistor 50 functions equivalently tothe first control switch 20 and the second control transistor 51functions equivalently to the second control switch 21.

The second switching circuit 5 has a third control transistor 52 and afourth control transistor 53. One end of the third control transistor 52is connected to an output line 7 of the P receiving differentialamplifier 2 and the other end thereof is connected to one end of thefirst mirror capacity 32. One end of the second control transistor 53 isconnected to a ground terminal GND and the other end thereof isconnected to one end of the second mirror capacity 32. Consequently, thethird control transistor 52 functions equivalently to the third controlswitch 22 and the fourth control transistor 53 functions equivalently tothe fourth control switch 23.

Because the control switches 20 to 23 are replaced with the controltransistors 50 to 53, the number of time constants can be increased,thereby the frequency characteristic can be improved. Transistors havinghigh ON resistance respectively should preferably be used as the firstand third control transistors 50 and 52 while transistors having low ONresistance respectively should preferably be used as the second andfourth control transistors 51 and 53. This is because the first controltransistor 20 and the first zero-point erasing resistor 40 in the secondembodiment can be replaced with the first control transistor 50 and thethird control switch 22 and the second zero-point erasing resistor 41can be replaced with the third control transistor 52. After thosereplacements, the frequency characteristic of the operational amplifierscan further be improved.

The operations of the control transistors 50 to 53 are the same as thoseshown in FIG. 5 in the first embodiment. As described above, also inthis case, the through-current is suppressed and the through-rate ofeach operational amplifier is prevented from lowering.

As described above, according to the present invention, a control switchis provided between a mirror capacity and the gate of an outputtransistor so that the mirror capacity is separated from the gate of atransistor of which ON resistance should not be lowered at the time ofpolarity inversion of the output voltage. Thus the gate voltage is keptconstant and the through-current is reduced, thereby the through-rate ofthe operational amplifier can be improved.

Furthermore, another control switch is provided at a terminal of themirror capacity connected to the gate of each output transistor. Whenthe gate of the transistor is separated from the mirror capacity, themirror capacity connected to a P channel transistor is connected to apower supply while the mirror capacity connected to an N channeltransistor is connected to a ground terminal. Consequently, when theoutput polarity is inverted next time and the gate of the disconnectedtransistor is connected to the mirror capacity again, it is possible toprevent the conventional problem that the charge accumulated in themirror capacity causes the gate voltage to be changed and the systemoperation to become unstable.

Thus the operational amplifier according to the present invention can beused favorably as an output circuit for driving the liquid crystalsubjected to voltage-follower connection. And because thethrough-current is reduced as described above, heat generation andelectromagnetic wave interference (EMI) of chips can be reduced.

It is apparent that the present invention is not limited to the aboveembodiments, but may be modified and changed without departing from thescope and spirit of the invention.

1. An amplifier, comprising: first and second output transistorsconnected serially between a first power supply potential and a secondpower supply potential; an output terminal connected to a node betweensaid first and second transistors; a first capacity element including afirst end coupled to said output terminal; a second capacity elementincluding a first end coupled to said output terminal; a first switchingcircuit for connecting a second end of said first capacity element tosaid first power supply potential or to said control terminal of saidfirst transistor; and a second switching circuit for connecting a secondend of said second capacity element to said second power supplypotential or to said control terminal of said second transistor.
 2. Theamplifier as claimed in claim 1, wherein said first switching circuitincludes: a first control switch provided between said second end ofsaid first capacity element and said control terminal of said firsttransistor; and a second control switch provided between said second endof said first capacity element and said first power supply potential;and wherein said second switching circuit includes a third controlswitch provided between said second end of said second capacity elementand said control terminal of said second transistor; and a fourthcontrol switch provided between said second end of said second capacityelement and said second power supply potential.
 3. The amplifier asclaimed in claim 2; wherein said amplifier further includes: a firstresistance element connected between said first control switch and saidsecond end of said first capacity element; and a second resistanceelement connected between said third control switch and said second endof said second capacity element.
 4. The amplifier as claimed in claim 2,wherein each of said first to fourth control switches is a MOStransistor.
 5. The amplifier as claimed in claim 2, wherein ONresistance of said first and third control switches is larger than thatof said second and fourth control switches.
 6. The amplifier as claimedin claim 1, wherein said amplifier further includes: a firstdifferential amplifier connected to said control terminal of said firsttransistor; and a second differential amplifier connected to saidcontrol terminal of said second transistor.
 7. The amplifier as claimedin claim 1, wherein a circuit that includes said first and second outputtransistors, said first and second capacity elements, and said first andsecond switching circuits is an AB class output circuit.
 8. A drivingcircuit, comprising: an amplifier according to claim 1; and a controlcircuit for controlling said first and second switching circuitsaccording to an inputted polarity inverted signal.
 9. A driving circuit,comprising: a plurality of operational amplifiers, each of saidoperation amplifiers configured with a voltage flower connection andincluding a pair of differential amplifiers and an amplificationcircuit, and wherein said amplification circuit includes: first andsecond output transistors connected serially between a first powersupply potential and a second power supply potential, a control terminalof said first output transistor being connected to one of said operationamplifiers, a control terminal of said second output transistor beingconnected to said the other of said operation amplifiers; an outputterminal connected to a node provided between said first and secondtransistors; a first capacity element having a first end connected tosaid output terminal; a second capacity element having a first endconnected to said output terminal; a first switching circuit connectinga second end of said first capacity element to said first power supplypotential or to said control terminal of said first transistor; and asecond switching circuit connecting a second end of said second capacityelement to said second power supply potential or to said controlterminal of said second transistor.
 10. The driving circuit as claimedin claim 9, wherein said first switching circuit connects said secondend of said first capacity element to said first power supply potentialand said second switching circuit connects said second end of saidsecond capacity element to said control terminal of said secondtransistor when polarity of an output of said output terminal isinverted from negative to positive; and wherein said first switchingcircuit connects said second end of said first capacity element to saidcontrol terminal of said first transistor and said second switchingcircuit connects said second end of said second capacity element to saidsecond power supply potential when polarity of an output of said outputterminal is inverted from positive to negative.
 11. The driving circuitas claimed in claim 9, wherein said first switching circuit includes afirst control switch provided between said second end of said firstcapacity element and said control terminal of said first transistor; anda second control switch provided between said second end of said firstcapacity element and said first power supply potential; and wherein saidsecond switching circuit includes a third control switch providedbetween said second end of said second capacity element and said controlterminal of said second transistor; and a fourth control switch providedbetween said second end of said second capacity element and said secondpower supply potential.
 12. The driving circuit as claimed in claim 9,wherein said driving circuit further includes: a first resistanceelement connected between said first control switch and said second endof said first capacity element; and a second resistance elementconnected between said third control switch and said second end of saidsecond capacity element.
 13. The driving circuit as claimed in claim 11,wherein each of said first to fourth control switches is a MOStransistor.
 14. The driving circuit as claimed in claim 13, wherein ONresistance of said first and third control switches is larger than thatof said second and fourth control switches.
 15. The driving circuit asclaimed in claim 9, wherein said amplification circuit is an AB classamplifier.
 16. The driving circuit as claimed in claim 9; wherein saiddriving circuit includes a control circuit that controls said controlswitches according to an input polarity inverted signal respectively.17. An amplifier, comprising: first and second output transistorsconnected serially between a first power supply potential and a secondpower supply potential; an output terminal connected to a node providedbetween said first and second transistors; and a first capacity elementprovided between a control terminal of said first transistor and saidoutput terminal; wherein said first capacity element and said controlterminal of said first transistor are electrically disconnected fromeach other when an output voltage of said output terminal is changedfrom a first level to a second level.
 18. The amplifier as claimed inclaim 17, said amplifier further comprising a second capacity elementprovided between a control terminal of said second transistor ad saidoutput terminal; wherein said second capacity element and said controlterminal of said second transistor are electrically disconnected fromeach other when an output voltage of said output terminal is changedfrom said second level to said first level.
 19. The amplifier as claimedin claim 18, wherein said first capacity element is electricallyconnected to said first power supply potential when an output voltage ofsaid output terminal is changed from said first level to said secondlevel.
 20. The amplifier as claimed in claim 19, wherein said secondcapacity element is electrically connected to said second power supplypotential when an output voltage of said output terminal is changed fromsaid second level to said first level.